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今日热门资讯
代公司发布几个招聘职位：
以下是借用以前的描述，以前各职位对经验要求较高，现在对工作经验放宽要求，应届生有相关的实习经历也欢迎应聘
如果有符合条件并感兴趣的，请mail 联系我：chao.liu@panovel.com
职位名称：物理层ASIC设计工程师
1． 职责：
(1) 与‘物理层系统工作组’合作提出物理层ASIC框图架构；
(2) 物理层算法的ASIC实现；
(3) 与‘MAC工作组’和‘固件组’合作完成‘物理层-MAC’接口；
(4) 物理层的FPGA验证和排错。
2． 资格：
(1) OFDM物理层实现的直接工作经验；
(2) OFDM物理层优化和排错的直接工作经验；
(3) 在ASIC设计流程，包括时序等方面有丰富经验。
3． 优先考虑:
有FPGA实现，无线通信IC设计经验者；硕士或以上学历。
职位名称：SoC ASIC 设计工程师
1． 职责
(1) 在UWB片上系统(SoC)上集成ARM处理器和AMBA总线；
(2) 设计DMA；
(3) 实现MAC功能，如排队管理；
(4) 与‘物理层ASIC工作组’和‘固件工作组’合作完成‘物理层-MAC’接口。
2． 资格
(1) 具有SoC设计的丰富经验；
(2) 具有ASIC设计流程的丰富；
(3) 具有ARM/AMBA集成的经验；
(4) 具有DMA设计经验；
(5) 在复杂FIFO管理方面有经验。
3． 优先考虑:
有以下经验者：ARM 集成，AMBA总线，DMA和MAC；硕士或以上学位。
职位名称：ASIC验证工程师
Position title: Senior ASIC Verification Engineer
1． Responsibilities:
1) Working within an ASIC design team to develop reusable block-level and ASIC testbenches using high-level verification
language (System Verilog).
2) Develop new ASIC verification environments to support ASIC development.
3) Review RTL architectural and implementation specifications.
4) Create stimulus drivers, monitors, dataflow models, and test plans to verify function and performance of advanced SOC
ASICs.
5) Define and implement code/functional coverage plans.
6) Develop testing and regression methodologies for new verification flow.
7) Incorporate reusability into all aspects of the verification environment.
8) Develop/maintain/enhance environment tools/scripts/makefiles.
2． Qualification:
1) Minimum of 3 years ASIC verification experience in a product development environment with proven ASIC design
verification skills
2) Experience in using event-driven simulators like VCS
3) Fluent in Verilog for design verification
4) Experience in writing testbench using System Verilog
5) Knowledge of peripheral IP intergration (PCI, USB2.0, PCI)
6) Knowledge of AMBA/AHB/DMA
7) Experience with one or more scripting languages: Perl, TCL, Shell
8) Superior debugging skills for large ASIC designs
9) Strong written and verbal communication skills
3． Required Degree: MS
Preferred Major: Electrical Engineering or related discipline
职位名称：数字后端设计工程师
Position title: Senior Digital Back-end Design Engineer
Responsibilities:
1) Responsible for developing and verifying complex digital designs with emphasis on backend tasks, including Floorplan,
power planning and routing, CTS, PnR, RC extraction, ECO, DRC, LVS.
2) Work with RTL designers to optimize timing/area/power of the physical design implementation and perform static timing
analysis.
Qualification:
1) 3-5 years experience in backend design flow with proven SOC tapeout experience.
2) Expertise in floorplan, place and routing, signal integrity, power analysis, CTS, DFT, ECO, DRC, LVS.
3) Experienced in Synopsys/Cadence) physical design tools and flows.
4) Experienced in Mentor’s Calibre flow for DRC/ERC/LVS/Antenna flow.
5) Strong timing analysis capabilities.
6) Experience with one or more scripting languages (Perl, TCL, Shell) to automate physical design flow.
7) Good analytical and debugging skills.
8) Strong written and verbal communication skills. |
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